1. Field of the Invention
The present invention relates to a technique for fabricating a semiconductor integrated circuit with a greater device density, and more particularly, to field-effect devices adapted for larger scales of integration and also to a method of fabricating such field-effect devices. A semiconductor device according to the invention is used especially advantageously as a nonvolatile semiconductor memory device having floating gates.
2. Description of the Related Art
Some conventional semiconductor devices are formed on a flat plane. Field-effect devices such as a MOS field-effect transistors (MOSFET) or a MISFET have a source, a drain, and a channel arranged substantially on a flat plane. The drain current is made to flow in a direction parallel to the substrate. In this planar device, however, limitations are imposed on the device area reduction as a matter of course. Therefore, in an attempt to obtain larger device densities, methods for manufacturing a planar device from plural layers and methods of fabricating a device structure itself in a form different from a planar structure have been discussed. An example of the latter methods includes a vertical-channel MOSFET proposed by us in Japanese Patent Unexamined Publication No. 13627/1994, which, in turn, corresponds to U.S. Pat. No. 5,350,937 and U.S. pending application Ser. No. 08/268,448, the disclosures of which are herein incorporated by reference. In particular, the drain is located over or under the source so that the drain current flows substantially vertically. This structure permits larger component densities.
The above-cited Japanese Patent Unexamined Publication No. 13627/1994 pertains to a nonvolatile semiconductor memory. Specifically, a floating gate and a control gate are formed by anisotropic etching on side surfaces of elevated portions which are formed on a semiconductor substrate. It is to be noted, however, only the fundamental device structure is shown. Neither the whole memory construction nor the fabrication process is described in detail. For example, with respect to its peripheral circuit, few mentions are made of its structure and fabrication process.
The present invention is intended to address the foregoing problems with the prior art technique.
It is an object of the present invention to provide an improved NAND-type nonvolatile memory.
A method of fabricating a semiconductor device in accordance with the present invention comprises the steps of:
(1) burying an insulator for isolating device components in a semiconductor device;
(2) etching the semiconductor substrate and the insulator to form elevated portions;
(3) depositing an insulating film on exposed surface portions of the semiconductor substrate;
(4) forming a first conductive film;
(5) etching the first conductive film selectively and isotropically;
(6) anisotropically etching the first conductive film to form floating gates on side surfaces of the elevated portions;
(7) forming an insulating film on surfaces of the floating gates;
(8) forming a second conductive film; and
(9) anisotropically etching the second conductive film to form control gates on the side surfaces of the elevated portions so as to cover the floating gates.
The processing steps (5) and (6) may be interchanged in order. A doping step for diffusing dopants that impart one conductivity type may be carried out at any time as long as this step is performed later than the processing step (2). Furthermore, if multilevel metallization is utilized in the same way as in the prior art technique, an interlayer insulator is deposited after the processing step (9), and the top layer of metallization may be deposited.
The processing step (1) may use LOCOS (localized oxidation of silicon). Also, trench isolation technology which has attracted attention as a new device isolation technology may also be employed. In the processing steps (3) and (7), the insulating films may be formed by thermal oxidation, thermal nitridation, or CVD.
The first conductive film deposited by the processing step (4) will become floating gates after etching. Generally, as a result of the anisotropic etching of the step (6), the first conductive continuous film is left on one side surface of each elevated portion. If plural devices should be formed on each one side surface, it is necessary to isolate the floating gates of one device from the floating gates of other devices. For this purpose, the processing step (5) is carried out. In the step (5), the first conductive film on the side surfaces of the elevated portions is selectively etched. Then, the anisotropic etching of the step (6) is effected to obtain floating gates for the individual devices on each one side surface.
As mentioned previously, the processing steps (5) and (6) can be interchanged in order, because these two etching steps are independent steps which do not affect each other.
Where only vertical channel-type devices are fabricated, the order in which the doping processes are carried out presents no serious problems. However, if doping is done between the steps (2) and (4), the side surfaces of the elevated portions where channels should be formed might be doped. Therefore, the doping is preferably done after the processing step (4). If planar MOSFETs are formed at the same time, the doping is preferably carried out after the end of the processing step (9). Thus, the source and drain regions of the planar MOSFETs can be self-aligned to the gates.
While the novel fabrication process of the present invention has been described thus far as related to general cases, special cases are next described. A NAND-type nonvolatile memory is a promising application of the present invention. Where the novel fabrication process is applied to this NAND-type nonvolatile memory, care must be paid to device isolation technology. The technique of the above-cited Japanese Patent Unexamined Publication No. 13627/1994 is not limited to a NAND circuit. The NAND circuit has. the disadvantage that ground lines must be laid parallel to the bit lines. However, the number of contacts to the top layer of metallization (in the case of a NAND circuit, bit lines and ground lines) per memory cell can be reduced.
In an ordinary NAND circuit, each individual memory block is composed of four or more, preferably eight or more, memory cells, or memory transistors. Each block is equipped with 2 selecting transistors. There exists one contact which brings the bit line into contact with the source of each selecting transistor, i.e., there are 2 contacts per block. The number of the contacts per block can be reduced to 1 by making any two adjacent blocks share a common contact. Where each block is composed of 4 or 8 memory cells, the number of the contacts per memory cell is xc2xc or xe2x85x9, respectively. On the other hand, in a normal matrix memory circuit, ground lines can be formed on a substrate and so the top layer of metallization can be formed into only bit lines, but at least one contact is necessary for each one memory cell. In this way, increasing the number of contacts makes it difficult to realize a higher device density.
The application of the present invention to a NAND circuit starts with the processing step (1), i.e., device isolation. During this processing step, an insulator used for the device isolation is required to be buried in a direction parallel to the bit lines. During the step (2), it is necessary to form trenches (i.e., linear elevated portions) parallel to the word lines. Let D be the depth of the insulator used for the device isolation in the processing step (1). Let d be the etch depth during the process step (2). The following relation must be met:
Dxe2x88x92d greater than 0
This means that the bottom of the insulator is located deeper than the etching depth; otherwise device components would be coupled together in the direction of the word lines through the trenches formed by the processing step (2).
The device isolation is required for each bit line. Therefore, the insulator for the isolation used for the process step (1) is defined at regular intervals according to each bit line. In the present invention, two devices are formed per linear elevated portion and so two word lines are formed per linear elevated portion. Since the word lines intersect the bit lines, the insulator intersects the linear elevated portions or trenches.
In the NAND circuit, selecting transistors which are normal transistors having no floating gates must be formed at the same time. In the present invention, this requirement poses no problems. For example, if vertical-channel type selecting transistors are fabricated, the first conductive film is fully removed from the portions where the selecting transistors should be formed in the process step (5). Accordingly, any extra step is not needed to form the selecting transistors. If planar MOSFETs are used as the selecting transistors, these MOSFETs all become normal transistors having no floating gates because the first conductive film is etched off from the portions where the planar MOSFETs are formed, by the step (6). The planar MOSFETs are fabricated by a method described later.
Where the NAND circuit is composed of selecting transistors consisting of vertical-channel MOSFETs, the cross-section of the portion around the selecting transistors take the following shape, it being noted that details of the shape are described in Embodiment 2. Each selecting transistor is formed on a second elevated portion. Each memory cell is formed on first and third elevated portions. It is assumed that the first, second, and third elevated portions are arrayed in this order from the left. In this memory block, the right and left halves which are located on opposite sides of the second elevated portion are different from each other. A floating gate exists on the side surface of each of the first and third elevated portions. No floating gate resides on the second elevated portion.
Of course, a gate (in the case of a selecting transistor) or control gate (in the case of a memory cell) is present on each side surface of the elevated portions. Obviously, floating gates, gates, or control gates are formed by anisotropic etching.
Of course, the floating gates in one memory cell are electrically isolated from the floating gates in other memory cells. An interlayer insulator plates out on these elevated portions, control gates, and gates. Furthermore, bit lines and ground lines extending so as to intersect the control gates and gates are formed on the interlayer insulator.
The NAND circuit is characterized in that the bit lines and ground lines make contact not with the first and third elevated portions but with the second elevated portion on which the selecting transistors are formed. Similar memory cells exist on the left side of each first elevated portion and the right side of each third elevated portion. The elevated portions of selecting transistors of a structure similar to the second elevated portions form one memory block.
The whole memory matrix is constructed as described below. Two kinds of elevated portions are found on a cross section vertical to the word lines; one kind has a floating gate, while the other kind has no floating gate and constitutes a selecting transistor. Either kind has a gate or control gate. An interlayer insulator plates out on these elevated portions, control gates, or gates. Bit lines and ground lines are formed on this interlayer insulator. The bit and ground lines make contact with the latter elevated portions but not with the former elevated portions.
Where a semiconductor device is fabricated by making use of the present invention, some devices may be required to be fabricated by the conventional planar technology. In the present invention, in principle, the second conductive film is fully etched away, excluding the side surfaces of the elevated portions. Therefore, it is difficult to bring the control gates into contact with the top layer of metallization unless any appropriate measure is taken. In consequence, after the processing step (8), a process step for selectively masking the second conductive film is performed.
After this step (8), if the anisotropic etching of the step (9) is carried out, these masked portions are not etched away. More specifically, as a result of the process step (9), the side surfaces of the elevated portions or the unmasked portions of second conductive film are etched away. The gates and conductive interconnects of the planar MOSFET and the contact-forming portions at the ends of the control gates should be masked.
The source and drain of the planar MOSFET are formed after the formation of the gate, i.e., after the processing step (9). Where the planar MOSFET is formed in the portion etched by the processing step (2), the following requirement must be satisfied:
Dxe2x88x92d greater than xcex4
where D is the depth of the insulator for device isolation used by the step (1), xcex4 is the effective depth of the source and drain, and d is the etch depth achieved by the step (2). This means that in a portion formed by the step (2), the bottom of the insulator is located deeper than the bottoms of the source and drain; otherwise the bottoms of the source and drain would become deeper than that of the insulator, making it impossible to isolate the individual device components.
Irrespective of the location where planar MOSFET is formed, the following requirement must be met:
d greater than xcex4
Otherwise, the impurities would diffuse even below the elevated portions, thus making it substantially impossible to form the vertical channel.
Where a planar MOSFET is fabricated in addition to a vertical-channel device, one photolithography step is added. An example of circuit fabrication by this method is described in Embodiment 3. In processing step (6), the first conductive film formed on a plane is fully etched away unless the film is masked. Therefore, floating gates cannot be formed on the planar MOSFET.
Another method of fabricating a planar MOSFET is characterized in that a processing step for selectively masking the first conductive film is performed between the processing steps (4) and (5). In this case, the steps (5) and (6) cannot be interchanged in order. In this method, the gates and conductive interconnects of the planar MOSFET can be fabricated from the first conductive film. In practice, however, the gate interconnects of planar MOSFETs (which are mainly in the peripheral circuit) and the control gates of a memory are preferably made from the same film. Because of problems with the contacts of the control gates to the top layer of metallization, the above-described additional processing step makes it difficult to form a contact region.
In this case, a doping step may be carried out at any time if the processing step (6) has been already performed. As a result of the step (9), sidewalls are formed on the side surfaces of the gates and interconnects of the planar MOSFET. Utilizing this, a double drain can be formed by performing a doping step with two different doses. An example of circuit fabrication by this method is described in Embodiment 4.
A further method of fabricating a semiconductor device according to the invention has the following processing steps:
(11) etching the semiconductor substrate to form elevated portions;
(12) forming an insulating film on exposed surface portions of the semiconductor substrate;
(13) forming a first conductive film;
(14) anisotropically etching the first conductive film to form film portions on side surfaces of the elevated portions which will become floating gates;
(15) forming an insulating film on surfaces of the floating gates;
(16) selectively oxidizing the semiconductor substrate and/or the first conductive film to obtain an oxide for device isolation;
(17) forming a second conductive film;
(18) selectively masking the second conductive film; and
(19) anisotropically etching the second conductive film to form control gates on side surfaces of the elevated portions so as to cover the floating gates and, at the same time, to obtain gates for planar MOSFETs.
The processing step (16) may be performed either between the steps (13) and (14) or between the steps (14) and (15). The doping step for diffusing dopants that impart one conductivity type is performed preferably after the step (19). Thus, the source and drain (or impurity regions) of the planar MOSFET can be self-aligned to the gate. In order to obtain multilevel metallization in the same way as in the prior art technique, an interlayer insulator is deposited after the processing step (19), and the top layer of metallization may be deposited.
During the step (16), LOCOS or its technical extension may be exploited. In the processing steps (12) and (15), the insulating films may be formed by thermal oxidation, thermal nitridation, or CVD.
The first conductive film formed by the processing step (13) becomes floating gates after the etching step (14). Generally, as a result of the anisotropic etching of the step (14), the first conductive continuous film is left on one side surface of each elevated portion.
If plural devices should be formed on each one side surface, it is necessary to isolate the floating gates of one device from the floating gates of other devices. For this purpose, the processing step (16) is carried out to form an oxide for the device isolation and also to isolate the floating devices of one device from the floating devices of other devices.
As mentioned previously, the processing step (16) may be performed either between the steps (13) and (14) or between the steps (14) and (15). Each case is now discussed briefly. Where the step (16) is effected between the steps (13) and (14), the oxide for the device isolation first separates the first film, followed by the execution of the step (14) to form the floating gates on the side surfaces of the elevated portions. As a result, the floating gates of one device is separated from the floating gates of the adjacent device.
Where the step (16) is effected between the steps (14) and (15), selective oxidation brings an oxidation mask (usually made from silicon nitride) into direct contact with the semiconductor substrate and with the first conductive film and, therefore, there is the possibility that peeling takes place. However, this scheme is not unfeasible. For these reasons, the step (16) may be performed either between the steps (13) and (14) or between the steps (14) and (15).
While the novel fabrication process of the present invention has been described thus far as related to general cases, special cases are next described. A NAND-type nonvolatile memory is a promising application of the present invention. Where the novel fabrication process is applied to this NAND-type nonvolatile memory, care must be paid to device isolation technology. The technique of the above-cited Japanese Patent Unexamined Publication No. 13627/1994 is not limited to a NAND circuit. The NAND circuit has the advantage that the number of contacts to the top layer of metallization (in the case of a NAND circuit, bit lines; if necessary, ground lines are also included) per memory cell can be reduced compared to the prior art matrix circuit.
In a normal NAND circuit, each memory block is composed of 4 or more, preferably 8 or more, memory cells, or memory transistors, which are connected in series. At least two selecting transistors are arranged on opposite sides of each memory cell in each block. The source of each selecting transistor makes contact with each bit line at one location. That is, two contacts exist per block. The number of the contacts per block can be reduced to 1 by making any two adjacent blocks share a common contact. Where each block is composed of 4 or 8 memory cells, the number of the contacts per memory cell is xc2xc or xe2x85x9, respectively.
On the other hand, in a normal matrix memory circuit, each memory cell needs at least one contact. In this way, increasing the number of contacts makes it difficult to realize a higher device density.
In order to apply the present invention to a NAND circuit, the processing step (16) is first required to form plural kinds of oxides for device isolation in a direction substantially vertical to the word lines. Of course, in the process step (11), trenches are required to be formed parallel to the word lines. That is, linear elevated portions are necessitated.
The device isolation is not necessary between the memory cells connected in series or between the selecting transistors connected in series while it is necessary between the other transistors. During the step (16), the insulator for the device isolation is defined at regular intervals for the transistor arrays. In the present invention, two devices are formed on the side surfaces of each linear elevated portion. Therefore, two word lines are formed for one linear elevated portion. Since the word lines intersect the transistor arrays, the insulator for the device isolation intersects the linear elevated portions or trenches.
In the NAND circuit, selecting transistors which are normal transistors having no floating gates are necessary, together with memory cells. In the present invention, planar MOSFETs are used as the selecting transistors. Since those portions of the first conductive film on which the planar MOSFETs are fabricated are etched away by the step (14), all the planar MOSFETs become normal transistors having no floating gates.
It is necessary that the impurity regions of each selecting transistor contact the bit lines and ground lines. Where the selecting transistors are formed on the surfaces of the elevated portions, contact holes can be formed more advantageously than where the transistors are formed in trenches. A method of fabricating the planar MOSFETs is described later.
By making the selecting transistors the planar type, the formation of contacts on the elevated portions where vertical-channel devices are fabricated is dispensed with. This yields the following advantages. The width of the elevated portions where no contacts are required is designed with the minimum design rules. If contacts were necessary, its width would be at least twice as large as the minimum design rules.
Where semiconductor devices are fabricated, utilizing the present invention, some devices may be required to be fabricated in the peripheral circuit, by the conventional planar technology, as well as the selecting transistors. In the present invention, in principle, the second conductive film is fully etched away, excluding the side surfaces of the elevated portions. Therefore, it is difficult to bring the control gates into contact with the top layer of metallization unless any appropriate measure is taken. For this purpose, the processing step (18) is necessitated.
Following this step, if anisotropic etching of the step (19) is performed, then the masked portions are not etched. In particular, as a result of the step (19), the second conductive film, excluding the side surfaces of the elevated portions or the masked portions, is etched off. The gates and conductive interconnects of the planar MOSFET and the contact-forming portions at the ends of the control gates should be masked.
The source and drain of the planar MOSFET are formed after the formation of the gate, i.e., after the processing step (19). The doping step must satisfy the following requirement:
d greater than dxcex4
where d is the etch depth achieved by the step (11) and xcex4 is the effective depth of the source and drain.
Otherwise, the impurities would diffuse even below the elevated portions, thus making it substantially impossible to form the vertical channel.
Where a planar MOSFET is manufactured other than the vertical channel-type device in this way, one photolithography step is added. In the processing step (14), the first conductive film formed on a flat plane is fully etched away unless any mask is placed. Consequently, it is impossible to form floating gates on the planar MOSFET.
Other objects and features of the invention will appear in the course of the description thereof, which follows.